The present invention relates to a semiconductor integrated circuit device incorporating a spark killer diode which is suitable for protecting an output transistor.
For example, as shown in FIG. 11, a three-phase motor driver employs a circuit configuration in which pairs of series-connected transistors (Tr1 and Tr2, Tr3 and Tr4, Tr5 and Tr6) are connected in parallel between a DC power source VCC and the ground GND and in which output terminals provided between the pairs of transistors Tr1 and Tr2, Tr3 and Tr4, and Tr5 and Tr6 are connected to a motor M.
In the case of an inductive load as described above, electromotive forces are generated in forward and reverse directions when the motor is rotated and stopped. In the conventional art, protective diodes are connected between the collectors and emitters of the integrated series-connected transistors, and the diodes 4 are turned on when the potential at the output terminals becomes lower than the ground potential or higher than the potential VCC because of the electromotive force in the reverse direction to lead the electromotive force to a fixed potential, thereby protecting the interior of the integrated circuit including the series-connected transistors. Especially, when a current as great as several amperes is applied to the diodes 4, the diodes 4 are configured as separate components.
There are demands from users for integration of the diodes 4 in order to reduce the number of components of an apparatus. However, when diodes to which a current as great as several amperes is applied are integrated, a parasitic current is caused by a parasitic transistor effect which inevitably occurs in the integrated circuit, and this can cause a wattless current and can lead to latch-up in the worst case.
For example, the structure disclosed in Japanese patent publication No. H06-104459 was proposed as a structure for preventing a parasitic current.
Referring to FIG. 12, an N+ type buried layer 3 is provided between a P type semiconductor substrate 1 and an N type semiconductor substrate 2, and a P+ type isolating region 4 is diffused from a surface of the semiconductor layer 2 to the semiconductor substrate 1 such that it encloses the buried layer 3 to form an island 5. A P+ type buried layer 6 is formed on the buried layer 3 such that they partially overlap each other. An N+ type lead region 7 is provided such that it encloses the P+ type buried layer 6 and extends from a surface of the semiconductor layer 2 to the N+ type buried layer 3, and an N+ type diffused region 8 is formed in the enclosed region. Further, a P+ type lead region 9 is provided in the region enclosed by the lead region 7 such that it encloses the diffused region 8 and extends from the semiconductor layer 2 to the P+ type buried layer 6. Furthermore, a cathode 10 and an anode 11 are provided in the diffused region 8 and the P+ type lead region 9 respectively, and the anode 11 is electrically connected to the N+ type lead region 7.
That is, a diode is formed by the P+ type lead region 9 and the P+ type buried layer 6 serving as an anode region and the N type semiconductor region enclosed by the N+ type diffused region 8 and lead region 9 serving as a cathode region.
In such a diode element, a PNP type parasitic transistor Tr2 is formed by the N+ type buried layer 3 serving as the base, the P+ type buried layer 6 serving as the emitter, aid the P type semiconductor substrate 1 and P+ type isolating region 4 serving as the collector. Since the base and emitter of the parasitic transistor Tr2 is at the same potential through the connection of the anode, it is possible to prevent the parasitic PNP transistor from being turned on.
In the conventional semiconductor integrated circuit device described above, since electromotive forces in forward and reverse directions are generated when the motor is rotated and stopped in the case of an inductive load as shown in FIG. 11, protective diodes are connected between the collectors and emitters of the integrated series-connected transistors, and the diodes 4 are turned on when the potential at the output terminals becomes lower than the ground potential or higher than the potential VCC because of the electromotive force in the reverse direction to lead the electromotive force to a fixed potential, thereby protecting the interior of the integrated circuit including the series-connected transistors. Especially, when a current as great as several amperes is applied to the diodes 4, the diodes 4 are configured as separate components.
In order to satisfy demands for integration of the diodes 4 to achieve a reduction of the number of components of an apparatus, the diodes to which a current as great as several amperes is applied are integrated. In consideration to problems including a wattles current attributable to a parasitic current caused by a parasitic transistor effect which inevitably occurs in the integrated circuit, a structure as shown in FIG. 12 is employed in which diodes are incorporated in an IC.
Although the diodes 4 can be incorporated in an IC as described above, when the diodes 4 are off or when the cathodes 10 are at a voltage higher than the voltage at the anodes 11 in the structure shown in FIG. 12, it is necessary to provide a withstand voltage at which breakdown of the semiconductor device due to a breakdown current at the PN junction surface of the parasitic transistor TR1 can be avoided. Therefore, the width of the P+ type buried layer 6 as the base region of the parasitic transistor TR1 is small in the conventional structure, which has resulted in a problem in that a sufficient withstand voltage can not be maintained for the parasitic transistor TR1 because it is difficult to suppress an increase in a current amplification factor hfe.
The present invention has been made taking the above-described problem with the conventional art into consideration, and a semiconductor integrated circuit device according to the invention comprises: a semiconductor substrate of a first conductivity type; a first epitaxial layer of an opposite conductivity type formed on a surface of the substrate; a first buried layer of the first conductivity type constituted by a high concentration impurity diffusion layer formed to overlap with a first buried layer of the opposite conductivity type constituted by a high concentration impurity diffusion layer formed between the substrate and the first epitaxial layer; a second epitaxial layer of the opposite conductivity type formed on a surface of the first epitaxial layer; a second buried layer of the first conductivity type and a second buried layer of the opposite conductivity type constituted by a high concentration impurity diffusion layer formed between the first epitaxial layer and the second epitaxial layer; a diffused region of the first conductivity type constituted by a high concentration impurity diffusion layer that is diffused from a surface of the second epitaxial layer to the second buried layer of the first conductivity type; a first diffused region of the opposite conductivity type constituted by a high concentration impurity diffusion layer that is diffused from a surface of the second epitaxial layer to the second buried layer of the opposite conductivity type; a well region of the opposite conductivity type formed in the second epitaxial layer in a region surrounded by at least one of the diffused region of the first conductivity type and the second buried layer of the first conductivity type; and a second diffused region of the opposite conductivity type constituted by a high concentration impurity diffusion layer formed in an overlapping relationship with the well region, wherein the first buried layer of the first conductivity type and the second diffused region of the opposite conductivity type are separated in the direction of the depth.
In the semiconductor integrated circuit device according to the invention, preferably, the first buried layer of the first conductivity type and the first buried layer of the opposite conductivity type of the diode element are formed in an overlapping relationship, and the first buried layer of the first conductivity type and the diffused region of the first conductivity type are connected through the second buried layer of the first conductivity type. It has a structure in which the first buried layer of the first conductivity type and the second diffused region of the opposite conductivity type are spaced in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction whose junction surface is formed by the first buried layer of the first conductivity type and the first epitaxial layer in the diode element when the diode element is off and in which a withstand voltage to cope with a reverse bias state can be maintained by the depletion layer to prevent breakdown of elements in the device attributable to a breakdown current.
Preferably, the well region of the opposite conductivity type is formed in an overlapping relationship with the cathode lead region of the opposite conductivity type of the diode element. This makes it possible to provide a semiconductor integrated circuit device in which a forward voltage VBEF can be reduced because of a reduction in the resistance of an N type region at a PN junction when the diode element is off to improve a forward current (If) capacity of the device significantly.
In order to solve the above-described problem, a method of manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: providing a semiconductor substrate of a first conductivity type; diffusing an impurity in the substrate to form a buried layer of an opposite conductivity type in each of regions where a diode element, a vertical transistor of the first conductivity type, and a vertical transistor of the opposite conductivity type are to be formed; diffusing an impurity in the substrate to form a first buried layer of the first conductivity type in the diode element forming region in an overlapping relationship with the buried layer of the opposite conductivity type; forming a first epitaxial layer of the opposite conductivity type on the substrate; diffusing an impurity on the first epitaxial layer to form a second buried layer of the first conductivity type in each of the regions to form a diode element and a vertical transistor of the first conductivity type; forming a second epitaxial layer of the opposite conductivity type on the first epitaxial layer; diffusing an impurity on the second epitaxial layer to form a diffused region of the first conductivity type in the diode element forming region, thereby connecting the diffused region of the first conductivity type to the first buried layer of the first conductivity type through the second buried layer of the first conductivity type; diffusing an impurity on the second epitaxial layer to form well regions of the opposite conductivity type in the regions to form a diode element and a vertical transistor of the first conductivity type simultaneously; and forming a second diffused region of the opposite conductivity type in the well region in the diode element forming region.
Preferably, the step of forming the second buried layer of the first conductivity type in the diode element forming region is provided for connecting the first buried layer of the first conductivity type with the diffused layer of the first conductivity type, the step making it possible to keep the first buried layer of the opposite conductivity type and the diffused region of the opposite conductivity type at a great interval in the direction of the depth, thereby increasing a depletion layer forming region.